1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a dynamic random access memory or the like, and more preferably to a semiconductor memory device comprising hierarchically structured data lines.
2. Description of the Background Art
In high-density and large-volume semiconductor memory devices, such as a dynamic random access memory (hereinafter referred to as a DRAM) and the like, data is transferred between a memory cell and an I/O terminal using two kinds of wires having different wire loads, i.e., a bit line and a data line. The bit line is a wire having a sufficiently low wire load, which is used mainly to read/write a small amount of charge from/to a memory cell. The data line is a wire having a much larger wire load than that of the bit line, which is provided mainly on a memory array and is used to transfer data between the bit line and the I/O terminal.
FIG. 11 is a diagram showing a general structure of a semiconductor memory device. The semiconductor memory device of FIG. 11 comprises a plurality of memory cell groups 10a to 10n each including a plurality of memory cells 11, a plurality of sense amplifiers 12a to 12n, a plurality of column selection switches 13a to 13n, data line selection switches 21 and 22, a write buffer 23, and a read amplifier 24. Among them, the memory cell groups 10a to 10n, the sense amplifiers 12a to 12n and the column selection switches 13a to 13n constitute a memory array, while the data line selection switches 21 and 22, the write buffer 23 and the read amplifier 24 constitute a peripheral circuit 20. For example, data transfer between the memory cell 11 included in the memory cell group 10a and the input and output terminals DIN and DOUT is performed using bit lines BL0a to BL3a provided in the memory cell group 10a, global data lines DL0 and DL1 provided across the memory array, and a local data line LDL provided in the peripheral circuit 20.
To construct a large-volume and high-speed semiconductor memory device, it is necessary to cause the data line having a large wire load to operate with high speed. Conventionally, in order to cause the data line to operate with high speed, the following technique is widely used: a logically single data line is actually composed of two wires (hereinafter referred to as a data line pair), and a difference between complementary data flowing through the data line pair is detected and amplified. The lines BL0a to BL3a, the global data lines DL0 and DL1, and the local data line LDL of FIG. 11 are each composed of such a data line pair. Hereinafter, a method of precharging the data line pair will be described.
FIG. 12 is a diagram showing a structure of a conventional semiconductor memory device. FIG. 12 mainly shows a detailed structure of the peripheral circuit 20 of FIG. 11. In FIG. 12, the memory cell 11 is a cell for storing one-bit data. In accordance with signal EQBL and SE, the sense amplifier 12 amplifies data on bit line pairs BL0/NBL0 to BL3/NBL3 connected to the memory cell 11. In accordance with a write buffer control signal WB, the write buffer 23 writes data input from the input terminal DIN into the memory cell 11 via a local data line pair LDL/NLDL, global data line pairs DL0/NDL0 and DLl/NDL1, and the bit line pairs BL0/NBBL0 to BL3/NBL3. In accordance with a read amplifier control signal RA, the read amplifier 24 amplifies, with high speed, data on the global data line pairs DL0/NDL0 and DL1/NDL1 and the local data line pair LDL/NLDL, which has been read from the memory cell 11 and amplified by the sense amplifier 12.
The data line selection switches 21 and 22 connect no more than one of the two global data line pairs DL0/NDL0 and DL1/NDL1 with the local data line pair LDL/NLDL in accordance with data line selection signals DLSW0 and DLSW1. The column selection switch 13 connects no more than one of the two bit line pairs (e.g., BL0/NBL0, BL1/NBL1) with the global data line pair (e.g., DL0/NDL0) in accordance with column selection signals CSW0 and CSW1.
The semiconductor memory device 9 comprises three precharge circuits 91 to 93 for precharging the data line pairs for each bit of an input/output signal. The precharge circuits 91 to 93 each precharge a signal line in accordance with a precharge control signal EQDL. More specifically, the precharge circuit 91 precharges the global data line pair DL0/NDL0, the precharge circuit 92 precharges the global data line pair DL1/NDL1, and the precharge circuit 93 precharges the local data line pair LDL/NLDL. Thus, the semiconductor memory device 9 comprises the precharge circuits corresponding to the global data line pairs and the precharge circuit corresponding to the local data line pair.
A technique of precharging the data line in the semiconductor memory device 9 will be described with reference to FIG. 13. In the following description, it is assumed that a command (WRITE command) to write data “0” into a memory cell 11 connected to the bit line pair BL0/NBL0 (hereinafter referred to as a memory cell M0) is input at time Ta, and a command (READ command) to read data from a memory cell 11 connected to the bit line pair BL3/NBL3 (hereinafter referred to as a memory cell M3) is input at time Tb.
Before time Ta, the semiconductor memory device 9 is waiting for a command. In the command waiting state, the data line selection signals DLSW0 and DLSW1 are controlled to be in the inactive state (HIGH level), while the column selection signals CSW0 and CSW1 are also controlled to be in the inactive state (LOW level). Thereby, the local data line pair LDL/NLDL and the global data line pairs DL0/NDL0 and DL1/NDL1 are separated from each other. Also in the command waiting state, the precharge control signal EQDL is controlled to be in the active state (LOW level). Therefore, in the command waiting state, the local data line pair LDL/NLDL and the global data line pairs DL0/NDL0 and DL1/NDL1 are individually precharged to the HIGH level by the precharge circuits 91 to 93 while being separated from each other.
When the WRITE command is input at time Ta, the semiconductor memory device 9 is transitioned from the command waiting state to the command executing state. In this case, the precharge control signal EQDL is changed to the inactive state (HIGH level), resulting in stop of the operations of the precharge circuits 91 to 93. Therefore, the precharge of the local data line pair LDL/NLDL and the global data line pairs DL0/NDL0 and DL1/NDL1 is released, so that these signal lines become ready to be written with input data.
As a result of decoding an address designated by the WRITE command, the data line selection signal DLSW0 is changed into the active state (LOW level) and the column selection signal CSW0 is also changed into the active state (HIGH level). In addition to this, a word line WL0 is changed into the active state, so that the memory cell M0 is connected to the bit line pair BL0/NBL0. Thereby, data (e.g., “1”) stored in the memory cell M0 is amplified by the sense amplifier 12 before being read out onto the bit line pair BL0/NBL0. The write buffer 23 overwrites the data “1” read out onto the bit line pair BL0/NBL0 with the data “0” designated by the WRITE command. At this time point, the semiconductor memory device 9 completes the write process.
After completion of the write process, the local data line pair LDL/NLDL and the global data line pairs DL0/NDL0 and DL1/NDL1 are precharged again to be ready for the next operation. During the precharge of these signal lines, the data line selection signals DLSW0 and DLSW1 are controlled to be in the inactive state. Therefore, the local data line pair LDL/NLDL and the global data line pairs DL0/NDL0 and DL1/NDL1 are separated from each other and are precharged individually.
Next, when the READ command is input at time Tb, the semiconductor memory device 9 is transitioned from the command waiting state to the command executing state as in when the WRITE command is input. Also in this case, the precharge control signal EQDL is changed into the inactive state, so that the precharge of the local data line pair LDL/NLDL and the global data line pairs DL0/NDL0 and DL1/NDL1 is released.
As a result of decoding an address designated by the READ command, the data line selection signal DLSW1 is changed into the active state (LOW level) and the column selection signal CSW1 is also changed into the active state (HIGH level). In addition to this, the word line WL0 is changed into the active state, so that the memory cell M3 is connected to the bit line pair BL3/NBL3. Thereby, data (e.g., “0”) stored in the memory cell M3 is amplified by the sense amplifier 12 before being read out onto the bit line pair BL3/NBL3. The data is transmitted on the global data line pair DL1/NDL1 and the local data line pair LDL/NLDL to reach the read amplifier 24. Further, the read amplifier 24 amplifies the data read from the memory cell M3 and outputs the resultant data through the output terminal DOUT. At this time point, the semiconductor memory device 9 completes the read process.
After completion of the read process, the local data line pair LDL/NLDL and the global data line pairs DL0/NDL0 and DL1/NDL1 are precharged again to be ready for the next operation as in the completion of the write process.
As described above, the semiconductor memory device 9 comprises a bit line pair and two data line pairs (a local data line pair and a global data line pair) so as to transfer data between a memory cell and an I/O terminal. The two data line pairs are precharged individually while being separated from each other by the data line selection switches 21 and 22. Thus, by using a plurality of individual data line pairs to be precharged, the wire load of each data line is reduced, thereby making it possible to precharge the data line with high speed. The above-described technique of precharging a data line pair is generally used to achieve high-speed data transfer between a memory cell and an I/O terminal.
Another technique of precharging a data line pair has been known in which a power source circuit for a data line pair and a power source circuit for a sense amplifier are provided in a semiconductor memory device to separate an inner power source and an external power source (e.g., Japanese Patent Laid-Open Publication No. 2000-30455). According to this technique, even when current consumption during an operation of the sense amplifier changes a power source level and therefore the HIGH level of a bit line is changed, the precharge level of a data line follows that change, i.e., the data line precharge level itself is also changed. Therefore, data transfer between the bit line pair and the data line pair is not influenced by a change in the external power source and can be performed without error and with high speed.
However, the conventional semiconductor memory device comprises precharge circuits corresponding to the global data line pairs and the local data line pair. Therefore, the larger the number of precharge circuits, the larger the power consumption of the semiconductor memory device due to a charge/discharge current of a precharge control signal. Further, precharge circuits are laid out at intervals which are determined based on a bit line pitch, and therefore, the layout area is increased with an increase in the number of precharge circuits.
For example, in a semiconductor memory device in which one global data line pair is provided for two bit line pairs and one local data line pair is provided for four bit line pairs (FIG. 12), three precharge circuits are required for each bit of an input/output signal. Therefore, in this semiconductor memory device, the power consumption and the layout area are increased by an amount corresponding to the three precharge circuits. The increase of the power consumption and the layout area raises a particularly serious problem with a semiconductor memory device having a large input/output data width, such as an embedded DRAM included in a system-on-chip.